Stochastic memristor logic devices
US10748609B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2018 |
| Grant date | Aug 18, 2020 |
| Priority date | — |
| Expiry date | Apr 10, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/15
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In accordance with the present disclosure, one embodiment includes a memristor that is caused to be in a particular resistance state by a voltage applied across terminals of the memristor. A first logical input and a second logical input that are below a threshold voltage of the memristor are applied to a first terminal of the memristor. A first control input and a second control input are applied to a second terminal of the memristor. A logical output is determined based on a resistance state of the memristor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.