Time interleaved analog to digital converter with digital equalization and a reduced number of multipliers
US10749541B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2020 |
| Grant date | Aug 18, 2020 |
| Priority date | — |
| Expiry date | Jan 7, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/128
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital equalizer with reduced number of multipliers for correction of the frequency responses of an interleaved analog-to-digital-converter (ADC) is disclosed. An exemplary interleaved analog to digital converter with digital equalization includes at least one composite ADC including M time-interleaved sub-ADCs, and an equalization configuration deploying a Pre-FIR transformers unit, a FIRs assembly unit, and a Post-FIR transformers unit. The FIRs assembly unit includes a finite impulse response (FIR) filter network which is operative pursuant to a Fast Filtering Algorithm as an alternative to a conventional finite impulse response network, enabling a reduction of the number of multipliers compared to conventional FIR filter-based equalization networks for ADCs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.