Soft FEC with parity check
US10749629B2 · kind B2 · utility
6Cited by
2References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 3, 2019 |
| Grant date | Aug 18, 2020 |
| Priority date | — |
| Expiry date | May 3, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2001/0096
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present invention is directed to data communication systems and techniques thereof. More specifically, embodiments of the present invention provide an FEC encoder that generates parity symbols that are embedded into FEC blocks. An FEC decoder determines whether to perform error correction based on the parity symbols. When performing error correction, the decoder selects a worst symbol from a segment of symbols, and the worst symbol is corrected. There are other embodiments as well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.