Method and apparatus for simultaneous propagation of multiple clockfrequencies in serializer/deserializer (SerDes) Macros
US10749663B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2019 |
| Grant date | Aug 18, 2020 |
| Priority date | — |
| Expiry date | Sep 10, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The disclosed systems, structures, and methods are directed to a two wire-based clock multiplication unit (CMU), employing a first phase lock loop (PLL) configured to generate a first high-speed clock frequency f1 encoded in differential mode, a second PLL configured to generate a second high-speed clock frequency f2 encoded in common mode, and a summer configured to combine the differential mode encoding the first high-speed clock frequency f1 and the common mode encoding the second high-speed clock frequency f2 and transmit the combined differential and common mode high-speed clock frequencies on a two wire-based conductor bus. In addition, systems, structures, and methods directed to a two wire-based clock recovery module and a two wire-based clock recovery module have also been disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.