Duty cycle estimation
US10753966B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2018 |
| Grant date | Aug 25, 2020 |
| Priority date | — |
| Expiry date | Nov 30, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R29/023
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A duty cycle measuring circuit, the circuit comprising a synchronizer and a measurer, the synchronizer arranged such that when a signal to be measured comprising pulses having a pulse width and a pulse period is input to the synchronizer, synchronizing signals corresponding to each of pulse rising edge, pulse falling edge, pulse period start and pulse period end are output from the synchronizer, each synchronizing signal comprising a rising or falling edge, wherein the synchronizing signal outputs from the synchronizer are input to the measurer, and wherein the measurer is arranged to provide two measurement outputs based on the synchronizing signal inputs from the synchronizer, the measurement outputs comprising a first measurement output signal indicative of a pulse period measurement of the signal to be measured and a second measurement output signal indicative of a pulse width measurement of the signal to be measured.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.