Mechanism to enter or exit retention level voltage while a system-on-a-chip is in low power mode
US10754413B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2017 |
| Grant date | Aug 25, 2020 |
| Priority date | — |
| Expiry date | May 18, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing device, system and method. The computing device includes a memory storing instructions, and a processing circuitry coupled to the memory. The processing circuitry is configured to execute the instructions to process a first control signal and a second control signal from respective first and second control pins of a computing platform. The processing circuitry is further to transition the computing platform, based on a combination of the first control signal and the second control signal and using at least one voltage pin on the platform, between a low power state and a retention power state without transitioning to an operational power state in between.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.