Tiled switch matrix data permutation circuit
US10754621B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 30, 2018 |
| Grant date | Aug 25, 2020 |
| Priority date | — |
| Expiry date | Aug 30, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/2764
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure pertain to switch matrix circuit including a data permutation circuit. In one embodiment, the switch matrix comprises a plurality of adjacent switching blocks configured along a first axis, wherein the plurality of adjacent switching blocks each receive data and switch control settings along a second axis. The switch matrix includes a permutation circuit comprising, in each switching block, a plurality of switching stages spanning a plurality of adjacent switching blocks and at least one switching stage that does not span to adjacent switching blocks. The permutation circuit receives data in a first pattern and outputs the data in a second pattern. The data permutation performed by the switching stages is based on the particular switch control settings received in the adjacent switching blocks along the second axis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.