Translation of virtual addresses to physical addresses using translation lookaside buffer information
US10754790B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2018 |
| Grant date | Aug 25, 2020 |
| Priority date | — |
| Expiry date | Oct 31, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/683
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory management unit (MMU) is disclosed. The MMU is configured to receive a translation request from a processing system, wherein the translation request specifies a virtual address to be translated, search a page table stored in a physical memory system for a page table entry that specifies the virtual address, receive a translation lookaside buffer invalidation (TLBI) signal from the processing system, wherein the TLBI signal specifies the virtual address, in response to receiving the TLBI signal specifying the virtual address, invalidate a translation lookaside buffer (TLB) entry in a TLB, wherein the invalidated TLB entry specifies the virtual address and restart the search of the page table for the page table entry that specifies the virtual address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.