NOR memory cell with L-shaped floating gate
US10756100B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 5, 2018 |
| Grant date | Aug 25, 2020 |
| Priority date | — |
| Expiry date | Sep 5, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electrically erasable programmable nonvolatile memory cell includes a semiconductor substrate having a first substrate region and a second substrate region apart from the first substrate region in a lateral direction, a channel region between the first substrate region and the second substrate region, an electrically conductive control gate insulated from and disposed over a first channel portion of the channel region, an electrically conductive floating gate insulated from and disposed over a second channel portion of the channel region, an electrically conductive source line electrically connected to the second substrate region, and an electrically conductive erase gate insulated from and disposed over a tip of the floating gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.