Semiconductor device including partially enlarged channel hole
US10756107B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2018 |
| Grant date | Aug 25, 2020 |
| Priority date | — |
| Expiry date | Dec 1, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a lower stack structure on a substrate, an upper stack structure on the lower stack structure, and a channel structure in a channel hole formed through the upper stack structure and the lower stack structure. The channel hole includes a lower channel hole in the lower stack structure, an upper channel hole in the upper stack structure, and a partial extension portion adjacent to an interface between the lower stack structure and the upper stack structure. The partial extension portion is in fluid communication with the lower channel hole and the upper channel hole. A lateral width of the partial extension portion may be greater than a lateral width of the upper channel hole adjacent to the partial extension portion and greater than a lateral width of the upper channel hole adjacent to the partial extension portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.