Integrated ring oscillator clock generator
US10756710B2 · kind B2 · utility
1Cited by
15References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 11, 2018 |
| Grant date | Aug 25, 2020 |
| Priority date | — |
| Expiry date | Jul 25, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/86
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock generator includes a series of inverting stages; and at least one combinational logic stage. The series of inverting stages is tapped at two or more locations along the series of inverting stages to provide intermediary outputs. A combinational logic stage of the at least one combinational logic stage is coupled to receive two or more of the intermediary outputs and generate a clock signal. Multi-phase, multi-duty cycle, non-overlapping clock signals can be generated by the clock generator based on different combinations of intermediary outputs. The clock signals can be provided to a switching network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.