Systems with power transistors, transistors coupled to the gates of the power transistors, and capacitive dividers coupled to the power transistors
US10756726B2 · kind B2 · utility
1Cited by
11References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2018 |
| Grant date | Aug 25, 2020 |
| Priority date | — |
| Expiry date | Oct 1, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0081
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An example system comprises: a power transistor comprising a gate, a first terminal, and a second terminal; a transistor comprising a gate, a first terminal, and a second terminal coupled to the gate of the power transistor; a capacitive divider coupled to the first terminal of the power transistor and the gate of the transistor; and a resistive divider coupled to the first terminal of the power transistor and the gate of the transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.