Analog to digital convertor (ADC) using a common input stage and multiple parallel comparators
US10756747B2 · kind B2 · utility
1Cited by
7References
20Claims
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Key dates
| Filing date | Jul 1, 2019 |
| Grant date | Aug 25, 2020 |
| Priority date | — |
| Expiry date | Jul 1, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/462
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An Analog to Digital (ADC) is provided, where the ADC may include a sample and hold circuitry to sample an analog input signal, and a summation block to iteratively generate a subtraction signal. The subtraction signal may be based on a difference between the analog input signal and a feedback signal. The ADC may further include a common input stage to receive the subtraction signal, and a plurality of comparison and latch circuitries arranged in parallel, where individual ones of the plurality of parallel comparison and latch circuitries may sequentially receive an output of the common input stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.