Patent · US Active

Programmable receivers including a delta-sigma modulator

US10756751B2 · kind B2 · utility

0Cited by
5References
22Claims
0Family size

Assignee

Inventors

Key dates

Filing dateOct 31, 2018
Grant dateAug 25, 2020
Priority date
Expiry dateOct 31, 2038

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH04B1/38
  • WIPO fieldBasic communication processes
  • WIPO sectorElectrical engineering

Abstract

Various embodiments relate to an analog-to-digital converter (ADC). The ADC may include a first channel including a first delta-sigma loop filter and a second channel including a second delta-sigma loop filter. Each of the first delta-sigma loop filter and the second delta-sigma loop filter may include a first integrator and a quantizer having an input coupled to an output of the first integrator. Each of the first delta-sigma loop filter and the second delta-sigma loop filter may also include a first summing node having an output coupled to an input of the first integrator, and a feedforward path from an input of the delta sigma loop filter to a first input of the first summing node. Further, each of the first delta-sigma loop filter and the second delta-sigma loop filter may include a first feedback path from an output of the quantizer to a second input of the first summing node.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.