Clock fail detector
US10761558B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2020 |
| Grant date | Sep 1, 2020 |
| Priority date | — |
| Expiry date | Mar 6, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock fail detector is provided. The clock fail detector includes a timing control signal generator and a clock fail detection module, which may generate control signals according to a clock signal and perform clock fail detection according to the control signals, respectively. The clock fail detection module may comprise first integrators, sample and hold circuits, a second integrator and a comparator. The first integrator may convert previous periods of the clock signal into reference voltages according to ping pong mode control signals within the control signals, respectively. The sample and hold circuits may sample and hold the reference voltages according to the ping pong mode control signals. The second integrator may convert a current clock period of the clock signal into a ramp signal. The comparator may compare the ramp signal with a reference voltage to generate a comparison result signal for indicating whether the clock signal is normal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.