Clock gating enable generation
US10761559B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 1, 2017 |
| Grant date | Sep 1, 2020 |
| Priority date | — |
| Expiry date | May 12, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a clock-gating system for a pipeline includes a clock-gating device configured to gate or pass a clock signal to the pipeline, and a clock controller. The clock controller is configured to track a number of input packets at an input of the pipeline, to track a number of output packets at an output of the pipeline, to determine whether to gate or pass the clock signal based on the number of the input packets and the number of the output packets, to instruct the clock-gating device to pass the clock signal if a determination is made to pass the clock signal, and to instruct the clock-gating device to gate the clock signal if a determination is made to gate the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.