Methods and apparatus of cache access to a data array with locality-dependent latency characteristics
US10761988B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2018 |
| Grant date | Sep 1, 2020 |
| Priority date | — |
| Expiry date | Oct 2, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6082
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of the present disclosure relate to an apparatus comprising a data array having locality-dependent latency characteristics such that an access to an open unit of the data array has a lower latency than an access to a closed unit of the data array. Set associative cache indexing circuitry determines, in response to a request for data associated with a target address, a cache set index. Mapping circuitry identifies, in response to the index, a set of data array locations corresponding to the index, according to a mapping in which a given unit of the data array comprises locations corresponding to a plurality of consecutive indices, and at least two locations of the set of locations corresponding to the same index are in different units of the data array. Cache access circuitry accesses said data from one of the set of data array locations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.