Techniques to reduce read-modify-write overhead in hybrid DRAM/NAND memory
US10762000B2 · kind B2 · utility
7Cited by
2References
18Claims
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Key dates
| Filing date | Jul 27, 2017 |
| Grant date | Sep 1, 2020 |
| Priority date | — |
| Expiry date | Aug 31, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of choosing a cache line of a plurality of cache lines of data for eviction from a frontend memory, the method including assigning a baseline replacement score to each way of a plurality of ways of a cache, the ways respectively storing the cache lines, assigning a validity score to each way based on a degree of validity of the cache line stored in each way, assigning an eviction decision score to each way based on a function of the baseline replacement score for the way and the validity score for the way, and choosing a cache line of the way having a highest eviction decision score as the cache line for eviction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.