Matrix tiling to accelerate computing in redundant matrices
US10762035B1 · kind B1 · utility
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20Claims
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Key dates
| Filing date | Feb 8, 2019 |
| Grant date | Sep 1, 2020 |
| Priority date | — |
| Expiry date | Mar 7, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are provided for matrix tiling to accelerate computing in redundant matrices. The method may include identifying unique submatrices in the matrix; loading values of elements of each unique submatrix into a respective one of the array processors; applying the vector to inputs of each of the array processors; and adding outputs of the array processors according to locations of the unique submatrices in the matrix.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.