Memory devices
US10762947B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2019 |
| Grant date | Sep 1, 2020 |
| Priority date | — |
| Expiry date | Apr 19, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device is provided. The memory device receives a main clock signal and provides an internal main clock signal; a data clock buffer to receive a data clock signal; and a latency control circuit configured to generate latency information based on the data clock signal and provide the latency information to a data circuit. The latency control circuit includes: a divider configured to generate divided-by-two clock signals based on the data clock signal; a divider configured to generate divided-by-four clock signals based on a first group of the divided-by-two clock signals; a first synchronization detector configured to output divided-by-two alignment signals indicating whether a second group of divided-by-two clock signals is synchronized with the data clock signal; and a latency selector configured to detect phases of the divided-by-four clock signals based on the divided-by-two alignment signals and adjust a latency of the main clock signal based on the phases.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.