Semiconductor package and method of manufacturing the same
US10763242B2 · kind B2 · utility
1Cited by
6References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2018 |
| Grant date | Sep 1, 2020 |
| Priority date | — |
| Expiry date | Jan 29, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/1047
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a first layer of one or more first semiconductor chips each having a first surface at which one or more first pads are exposed, a second layer of one or more second semiconductor chips disposed over the first layer and each having a second surface at which one or more second pads are exposed, and a first redistribution layer between the first layer and the second layer and electrically connected to the one or more first pads. The first layer may include one or more first TPVs extending through a substrate (panel) of the first layer and electrically connected to the first redistribution layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.