Semiconductor memory device
US10763278B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 9, 2019 |
| Grant date | Sep 1, 2020 |
| Priority date | — |
| Expiry date | Jan 9, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a substrate having a cell array region and a contact region, a stack structure including a plurality of gate electrodes on the cell array region and the contact region, a plurality of cell vertical channel structures extending through the stack structure on the cell array region, and a contact structure disposed beside of the stack structure on a top surface of the substrate and disposed along a line extending from the cell array region toward the contact region. The height of the contact structure on the cell array region is different from the height of the contact structure on the contact region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.