Comparator circuit with hysteresis function and a semiconductor device thereof
US10763840B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2019 |
| Grant date | Sep 1, 2020 |
| Priority date | — |
| Expiry date | Oct 23, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/3565
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A comparator circuit includes a first comparator, a second comparator and an inverter. The first comparator includes two N-channel metal-oxide-semiconductor (NMOS) transistors, two first P-channel metal-oxide-semiconductor (PMOS) transistors and two second PMOS transistors. A gate of the NMOS transistors respectively receives first and second voltages, and sources of the first PMOS transistors are connected to first and second resistors, respectively. The first comparator outputs differential output signals from drains of the NMOS transistors according to the voltage difference between the first and second voltages. An output of the second comparator is connected to gates of the first PMOS transistors of the first comparator. An input of the inverter is connected to the output of the second comparator, and an output of the inverter is connected to gates of the PMOS transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.