Electronic circuit configured to adjust sampling timing for recovering data
US10763866B2 · kind B2 · utility
3Cited by
7References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2019 |
| Grant date | Sep 1, 2020 |
| Priority date | — |
| Expiry date | Jul 15, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0994
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An electronic circuit includes a clock recovery circuit that generates a first reference clock signal based on first reception data and generates a second reference clock signal based on second reception data received after the first reception, a sampling clock generator that generates a sampling clock signal having a phase based on a phase difference between the first reference clock signal and the second reference clock signal, and a sampler that recovers the second reception data based on the generated sampling clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.