Patent · US Active

Apparatuses and methods involving phase-error tracking circuits

US10763871B1 · kind B1 · utility

2Cited by

2References

20Claims

0Family size

Assignee

NXP B.V. · NL

Inventors

Manoj Kumar Patasani · Hamburg, DE
Tarik Saric · Eindhoven, NL
Juan Felipe Osorio Tamayo · Eindhoven, NL

Key dates

Filing date	Jul 3, 2019
Grant date	Sep 1, 2020
Priority date	—
Expiry date	Jul 3, 2039

Classification

Technology area (CPC H)Electricity
CPC primaryH04L27/12
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Embodiments are directed to apparatuses and methods involving a phase-error tracking circuit. An example apparatus includes a divide-by phase locked loop (PLL) circuit to generate a continuous wave signal that sweeps over a frequency range in response to a divider feedback signal and to a reference signal. The apparatus further includes the phase-error tracking circuit defining a phase-error window in which the divide-by PLL circuit is to lock based on a slope associated with a rate of change of the frequency range, and indicating whether a phase error between the divider feedback signal and the reference signal coincides with the phase-error window.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.