Calibrating time-interleaved switched-capacitor track-and-hold circuits and amplifiers
US10763878B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2019 |
| Grant date | Sep 1, 2020 |
| Priority date | — |
| Expiry date | Mar 25, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1245
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Background calibration techniques can effectively to correct for memory, kick-back, and order-dependent errors in interleaved switched-capacitor track-and-hold (T/H) circuits and amplifiers. The techniques calibrate for errors in both the track/sample phase and the hold-phase, and account for the effects of interleaving, buffer/amplifier sharing, incomplete resetting, incomplete settling, chopping, and randomization on the offset, gain, memory, and kick-back errors. Moreover, the techniques can account for order-dependent and state-dependent hold-phase non-linearities. By correcting for these errors, the proposed techniques improve the noise performance, linearity, gain/offset matching, frequency response (and bandwidth), and order-dependence errors. The techniques also help increase the speed (sample rate and bandwidth) and linearity of T/H circuits and amplifiers while simplifying the analog circuitry and clocking needed. These techniques comprehensively account for various memory, kick-back, and order-dependent effects in a unified framework.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.