High linearity digital-to-analog converter with ISI-suppressing method
US10763884B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2019 |
| Grant date | Sep 1, 2020 |
| Priority date | — |
| Expiry date | Jul 18, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/3026
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital-to-analog conversion circuit is used for converting a first digital input into a first analog output, and includes a segmentation circuit, a plurality of multi-bit dynamic element matching digital-to-analog converters (DEM DACs), and a combination circuit. The segmentation circuit applies segmentation to the first digital input to generate a plurality of code segments. The multi-bit DEM DACs convert the code segments into a plurality of DAC outputs, respectively, wherein the multi-bit DEM DACs include at least a first multi-bit DEM DAC and a second multi-bit DEM DAC, and the first multi-bit DEM DAC and the second multi-bit DEM DAC employ different DEM techniques. The combination circuit combines the DAC outputs to generate the first analog output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.