Clock transfer and filtering using digital clock phase information
US10764028B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2019 |
| Grant date | Sep 1, 2020 |
| Priority date | — |
| Expiry date | Jul 2, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital PLL, which can be a virtual PLL, can condition digital phase information, comprising phase modification requests, for transfer, jitter, and phase-noise filtering of clock information between a clock recovery unit and a clock generation unit associated with phase interpolators. The digital PLL can employ a set of accumulators, proportional and integral filter component, generator component, feedback path between the output and input of the digital PLL, and other digital signal processing components. The proportional and integral filter component can be configurable to set a loop damping factor and a loop bandwidth of the filter, based on respective parameters. Based on the filter output, the generator component can generate output phase information, comprising phase modification requests, that can be transmitted to another phase interpolator(s) associated with a transmitter or other component(s) of the device to facilitate generating a clock for the transmitter or other component(s).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.