Matrix normal/transpose read and a reconfigurable data processor including same
US10768899B2 · kind B2 · utility
6Cited by
19References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2019 |
| Grant date | Sep 8, 2020 |
| Priority date | — |
| Expiry date | Jan 29, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A configurable circuit configurable according to the data width of elements of a matrix is described that includes a memory array, logic to write a matrix to the memory array having elements with a data width which can be specified using configuration data, logic for a transpose read of the matrix as-written and logic for normal read of the matrix as-written. The memory array includes first and second read ports operable in parallel. Transpose read logic and normal read logic can be coupled to the first and second read ports, respectively, allowing transpose and normal read of a matrix simultaneously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.