Patent · US Active

Intelligent fail recognition

US10769334B2 · kind B2 · utility

0Cited by

2References

20Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Bryan G. Hickerson · Cedar Park, US
Mohamed Baker Alawieh · Austin, US
Brian L. Kozitza · Georgetown, US
John Richard Reysa · Austin, US
Erica Stuecheli · Austin, US

Key dates

Filing date	Nov 16, 2018
Grant date	Sep 8, 2020
Priority date	—
Expiry date	Dec 1, 2038

Classification

Technology area (CPC G)Physics
CPC primaryG06N20/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method, computer program product, and a fail recognition apparatus are disclosed for debugging one or more simulation fails in processor design verification that in one or more embodiments includes determining whether a prediction model exists; retrieving, in response to determining the prediction model exists, the prediction model; predicting one or more bug labels using the prediction model; determining whether a fix is available for the one or more predicted bug labels; and simulating, in response to determining the fix is available for the one or more predicted bug labels, the fix for the one or more predicted bug labels.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.