System and method for graph based verification of electronic circuit design
US10769335B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2019 |
| Grant date | Sep 8, 2020 |
| Priority date | — |
| Expiry date | Oct 29, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic design automation (EDA) tool for executing topological and functional checks on an electronic circuit design (ECD) includes a processor and a memory that stores the ECD, graphical rules, and filter rules for executing the checks. The processor generates a test graph based on the ECD, replaces stretchable nodes with nested networks in the test graph to generate extended graphs, and decouples real edges and functional edges of each extended graph to generate real graphs and functional graphs, respectively. Based on the graphical rules, the processor executes the topological checks on an input graph of the ECD to identify real sub-graphs from the input graph that are isomorphic to a real graph. The processor further generates functional sub-graphs by combining a functional graph with each real sub-graph, and based on the filter rules, further executes the functional checks on the functional sub-graphs to identify output graphs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.