Determining timing paths and reconciling topology in a superconducting circuit design
US10769344B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2019 |
| Grant date | Sep 8, 2020 |
| Priority date | — |
| Expiry date | Jul 22, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for determining timing paths and reconciling topology in a superconducting circuit design are provided. The design may include a first timing path having a first set of timing pins associated with a first timing constraint group including a first timing endpoint and a second timing endpoint. An example method includes processing the first timing constraint group to assign a first legal start time to the first timing endpoint and a second legal start time to the second timing endpoint. The method further includes inserting a first shadow element representing a first physically connected component on the timing path, where the first shadow element precedes the first timing endpoint or follows the second timing endpoint. The method further includes addressing any changes to the first legal start time or the second legal start time caused by an insertion of the first shadow element on the timing path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.