Method for detecting thinning of the substrate of an integrated circuit from its back side, and associated integrated circuit
US10770409B2 · kind B2 · utility
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15Claims
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Key dates
| Filing date | Aug 1, 2018 |
| Grant date | Sep 8, 2020 |
| Priority date | — |
| Expiry date | Aug 1, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/819
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated electronic circuit includes a semiconductor substrate with a semiconductor well that is isolated by a buried semiconductor region located under the semiconductor well. A vertical MOS transistor formed in the semiconductor well includes a source-drain region provided by the buried semiconductor region. Backside thinning of the semiconductor substrate is detected by biasing the vertical MOS transistor into an on condition to supply a current and then comparing that current to a threshold. Current less than a threshold is indicative that the semiconductor substrate has been thinned from the backside.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.