Switch circuit and high-speed multiplexer-demultiplexer
US10771056B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2019 |
| Grant date | Sep 8, 2020 |
| Priority date | — |
| Expiry date | Oct 22, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0054
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A switch circuit and a high-speed multiplexer-demultiplexer are provided. The switch circuit includes an equalization module and an MOS transistor. A gate of the first MOS transistor is connected to an output terminal of the equalization module. An input terminal of the first MOS transistor is connected to a signal source. An output terminal of the first MOS transistor is connected to a subsequent circuit. The equalization module is configured to: supply a turning-on signal to the first MOS transistor in a case that an operation signal is acquired, to turn on the first MOS transistor; and generate a compensation signal for compensating an attenuation of the signal transmitted through the first MOS transistor, and apply the compensation signal to the gate of the first MOS transistor. The switch circuit operates in response to the operation signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.