Apparatus and method for an all-digital phase lock loop
US10771234B2 · kind B2 · utility
0Cited by
2References
9Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 28, 2018 |
| Grant date | Sep 8, 2020 |
| Priority date | — |
| Expiry date | Sep 28, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04W56/001
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may receive an otw signal that is associated with low-path pass information and transmission data. The apparatus may apply a cost function and an update function to the otw signal prior to sending the otw signal to an oscillator. The apparatus may determine a correction factor for use in estimating a gain of the oscillator based at least in part on an output of the update function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.