Optimized architecture for a signal decoder
US10771292B2 · kind B2 · utility
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14References
13Claims
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Key dates
| Filing date | May 31, 2019 |
| Grant date | Sep 8, 2020 |
| Priority date | — |
| Expiry date | May 31, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03426
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A device for determining a received signal as minimum values of a set of values, the device comprising a processor configured to: load a first set of values in a register; identify a maximum value of the first set of values and a minimum value of the first set of values; in the register, replace the maximum value by a value of a second set of values and simultaneously replace the minimum value by a new value, calculated based on the minimum value, to receive an updated first set of values; and repeat previous steps until all values of the updated first set of values are replaced by values of the second set of values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.