System and method for maintaining cache coherency
US10775870B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 7, 2018 |
| Grant date | Sep 15, 2020 |
| Priority date | — |
| Expiry date | May 7, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing device includes multiple processing units and multiple memory devices respectively assigned to the multiple processing units. Each of the multiple processing units includes a cache memory configured to retain data stored in the memory device assigned to itself, and fetched data taken out from the memory device of the processing unit other than itself. When an access request for the fetched data is received from a source processing unit from which the fetched data has been taken out, the cache memory determines occurrence of a crossing in which the access request is received after the cache memory issues write back information instructing to write back the fetched data to the memory device assigned to the source processing unit. If the crossing has occurred, crossing information indicating that the crossing has occurred is output as a response to the access request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.