Lock-free datapath design for efficient parallel processing storage array implementation
US10776012B2 · kind B2 · utility
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16Claims
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Key dates
| Filing date | May 19, 2017 |
| Grant date | Sep 15, 2020 |
| Priority date | — |
| Expiry date | Jan 9, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0688
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods (including hardware and software) are disclosed for us in a multi-core, multi-socket server with many RDMA network adapters and NVME solid state drives. One of the features of the subject matter is to optimize the total IO throughput of the system by first replacing software locks with non-interruptible event handlers running on specific CPU cores that own individual software data structures and hardware queues, and second by moving work to that CPU affinity without stalling due to software lock overhead.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.