Microprocessor with dynamically adjustable bit width for processing data
US10776109B2 · kind B2 · utility
2Cited by
9References
18Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 18, 2018 |
| Grant date | Sep 15, 2020 |
| Priority date | — |
| Expiry date | Dec 19, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor with dynamically adjustable bit width is provided, which has a bit width register, a datapath, a statistical register, and a bit width adjuster. The bit width register stores at least one bit width. The datapath operates according to the bit width stored in the bit width register to acquire input operands from received data and process input operands. The statistical register collects calculation results of the datapath. The bit width adjuster adjusts the bit width stored in the bit width register based on the calculation results collected in the statistical register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.