Instruction translation circuit, processor circuit and executing method thereof
US10776116B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2018 |
| Grant date | Sep 15, 2020 |
| Priority date | — |
| Expiry date | Oct 13, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30181
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An instruction translation circuit, a processor circuit, and an executing method thereof are provided. The instruction translation circuit is adapted for being disposed in the processor circuit. The instruction translation circuit includes a formatted instruction queue, a first instruction translator, an instruction detection circuit, and a second instruction translator. The formatted instruction queue stores a plurality of formatted macro instructions. The first instruction translator translates a first formatted macro instruction of the formatted macro instructions and outputs a first micro instruction. When the instruction detection circuit determines that a trap bit in the first formatted macro instruction is set and a part of the first formatted macro instruction can be translated in advance, the instruction detection circuit outputs first trap information. The second instruction translator translates the part of the first formatted macro instruction in advance according to the first trap information to output a second micro instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.