Patent · US Active

Bandwidth controlled data synchronization for image and vision processor

US10776167B2 · kind B2 · utility

3Cited by

1References

16Claims

0Family size

Assignee

TEXAS INSTRUMENTS INCORPORATED · US

Inventors

Niraj Nandan · Plano, US
Hetul Sanghvi · Bengaluru, IN
Mihir Narendra Mody · Kanchinakote, IN

Key dates

Filing date	Sep 19, 2016
Grant date	Sep 15, 2020
Priority date	—
Expiry date	May 31, 2037

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A hardware thread scheduler (HTS) is provided for a multiprocessor system. The HTS is configured to schedule processing of multiple threads of execution by resolving data dependencies between producer modules and consumer modules for each thread. Pattern adaptors may be provided in the scheduler that allows mixing of multiple data patterns across blocks of data. Transaction aggregators may be provided that allow re-using the same image data by multiple threads of execution while the image date remains in a given data buffer. Bandwidth control may be provided using programmable delays on initiation of thread execution. Failure and hang detection may be provided using multiple watchdog timers.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.