DDR5 RCD interface protocol and operation
US10776293B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 2018 |
| Grant date | Sep 15, 2020 |
| Priority date | — |
| Expiry date | Sep 14, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus including a host interface and a registered clock driver interface. The host interface may be configured to receive an enable command from a host. The registered clock driver interface may be configured to perform power management for a dual in-line memory module, generate data for the dual in-line memory module, communicate the data, receive a clock signal and communicate an interrupt signal. The registered clock driver interface may be disabled at power on. The registered clock driver interface may be enabled by in response to the enable command. The apparatus may be implemented as a component on the dual in-line memory module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.