Non-volatile memory device and method of erasing the same
US10777279B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2018 |
| Grant date | Sep 15, 2020 |
| Priority date | — |
| Expiry date | Nov 21, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/5671
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory device includes a substrate; a memory cell array on the substrate; a control logic circuit configured to output an erase enable signal for controlling an erase operation with respect to the memory cell array; a substrate bias circuit configured to, in response to the erase enable signal, output a first target voltage to the substrate as a substrate bias voltage during a first delay time and, after the first delay time, output the substrate bias voltage to the substrate while gradually increasing a level of the substrate bias voltage to that of an erase voltage having a higher level than the first target voltage; and a row decoder configured to apply a ground voltage to the ground select line based on control of the control logic circuit during the first delay time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.