Semiconductor device sub-assembly
US10777494B2 · kind B2 · utility
Assignees
Inventor
Key dates
| Filing date | Jan 23, 2017 |
| Grant date | Sep 15, 2020 |
| Priority date | — |
| Expiry date | Jan 23, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/13091
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
We disclose herein a semiconductor device sub-assembly comprising: a plurality of semiconductor units laterally spaced to one another; a plurality of conductive blocks, wherein each conductive block is operatively coupled with each semiconductor unit; a conductive malleable layer operatively coupled with each conductive block, wherein the plurality of conductive blocks are located between the conductive malleable layer and the plurality of semiconductor units. In use, at least some of the plurality of conductive blocks are configured to apply a pressure on the conductive malleable layer, when a predetermined pressure is applied to the semiconductor device sub-assembly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.