Integrated circuit comprising a chip formed by a high-voltage transistor and comprising a chip formed by a low-voltage transistor
US10777513B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 2017 |
| Grant date | Sep 15, 2020 |
| Priority date | — |
| Expiry date | May 26, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2017/6875
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit comprises a housing, a plurality of connection pins, a first chip that includes a high-voltage depletion mode transistor, and a second chip that includes a low-voltage enhancement mode transistor. The first chip and second chip each comprise a gate bump contact, a drain bump contact and a source bump contact. The source bump contact of the high-voltage transistor is electrically connected to the drain bump contact of the low-voltage transistor so as to form a central node of the circuit. The circuit includes at least one first Kelvin pin that is electrically connected to the source bump contact of the low-voltage transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.