Patent · US Active

Face-to-face three-dimensional integrated circuit of simplified structure

US10777537B2 · kind B2 · utility

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12Claims
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Assignee

Inventors

Key dates

Filing dateFeb 6, 2019
Grant dateSep 15, 2020
Priority date
Expiry dateFeb 6, 2039

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2225/06589
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

An integrated circuit including a first chip including a stack of a substrate, of an active layer and of interconnect layers; a second chip including a stack of a substrate, of an active layer and of interconnect layers; an interconnect network for interconnecting the first and second chips. The interconnect layer of the highest metallization level of the first chip includes a power distribution network; the interconnect layer of the highest metallization level of the second chip is without a power distribution network.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.