Seal-ring structure for stacking integrated circuits
US10777539B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2019 |
| Grant date | Sep 15, 2020 |
| Priority date | — |
| Expiry date | Sep 26, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/24145
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional (3D) integrated circuit (IC) die is provided. In some embodiments, a first IC die comprises a first semiconductor substrate, a first interconnect structure over the first semiconductor substrate, and a first hybrid bond (HB) structure over the first interconnect structure. The first HB structure comprises a HB link layer and a HB contact layer extending from the HB link layer to the first interconnect structure. A second IC die is over the first IC die, and comprises a second semiconductor substrate, a second HB structure, and a second interconnect structure between the second semiconductor substrate and the second HB structure. The second HB structure contacts the first HB structure. A seal-ring structure is in the first and second IC dies. Further, the seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate, and is defined in part by the HB contact layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.