Method of fabricating thin film transistor, thin film transistor, array substrate, and display apparatus
US10777588B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 13, 2018 |
| Grant date | Sep 15, 2020 |
| Priority date | — |
| Expiry date | Aug 13, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K85/221
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present application provides a method of fabricating a thin film transistor. The method includes selecting a nano-structure material having a monotonic relationship between a threshold voltage and a channel length when the nano-structure material is formed as a channel part in a thin film transistor; forming an active layer using the nano-structure material; determining a nominal channel length of a channel part of the thin film transistor based on the monotonic relationship and a reference threshold voltage so that the thin film transistor is formed to have a nominal threshold voltage; and forming a source electrode and a drain electrode thereby forming the channel part in the active layer having the nominal channel length.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.