CMOS image sensor with compact pixel layout
US10777601B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2020 |
| Grant date | Sep 15, 2020 |
| Priority date | — |
| Expiry date | Jun 16, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/778
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An image sensor array of shared pixel units fabricated by a CMOS technology, wherein each pixel unit includes a plurality of photodiodes and respective transfer transistors and floating drains whose layout constitutes mirror images. The plurality of photodiodes each share a single reset transistor and source follower amplifier transistor wherein the shared floating diode is spaced at the minimum distance from a gate electrode of the source follower transistor as is allowed by the CMOS fabrication technology chosen to manufacture the image sensor array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.