Reducing power consumption in a processor circuit
US10778196B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 19, 2019 |
| Grant date | Sep 15, 2020 |
| Priority date | — |
| Expiry date | Dec 19, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0016
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure pertain to reducing power consumption in a processor circuit. In one embodiment, a processor circuit comprises a plurality of data storage modules. The plurality of data storage modules each include one or more first multibit flip flop circuits having a first power consumption per bit and one or more second flip flop circuits having a second power consumption per bit. The first multibit flip flop circuits may have more bits than the second flip flop circuits. Additionally, the first power consumption per bit may be less than the second power consumption per bit such that power consumption is reduced when the first multibit flip flop circuits are used to store bits that change with a higher frequency than bits stored in the second flip flop circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.